This invention relates generally to the field of semiconductor electronics. More particularly, this invention relates to making semiconductor electronics less vulnerable to radiation. Even more particularly, this invention relates to reducing the vulnerability of latches to single event upsets.
When an particle with sufficient energy passes through a semiconductor it creates electron-hole pairs along its path. If the electron-hole pairs occur in a sensitive region, such as the drains of N-type or P-type FETs, the electron-hole pairs generate a current that temporarily changes the voltage at the drain node in an occurrence called a xe2x80x9cglitch.xe2x80x9d After a xe2x80x9crecovery time,xe2x80x9d the electrons and holes generated by the passage of the particle are absorbed or carried away and the drain voltage returns to normal.
A glitch can be particularly disruptive to memory cells or latch circuits. Such circuits have feedback paths through which a glitch can be reinforced and stabilized before the node""s recovery time has elapsed causing the node to stabilize in the glitch-induced state. Such an event is referred to as a single event upset or xe2x80x9cSEU.xe2x80x9d
The latch circuit illustrated in FIG. 1 is an example of a circuit that is susceptible to an SEU. A Data signal is applied to Data terminal 102, which is coupled to the gates of P-type FET 104 and N-type FET 106. These FETs perform a buffer function isolating the input Data signal from the loads required to operate the flip flop. If the input Data signal is high (as that term is understood by persons of ordinary skill in the art) then FET 106 turns on pulling node 108 low. If Data is low, FET 104 turns on pulling node 110 high.
The signal GB (gate bar) determines whether the flip flop holds its current state (GB high) or tracks the input Data signal (GB low). FET""s 112, 114, 116 and 118 are gating logic that configure the flip flop for storage (holding current state) or tracking, and FET""s 120, 122, 124 and 126 are a pair of inverters (128 and 130, respectively) that accomplish the storage function.
With GB low, FET""s 112 and 114 are xe2x80x9conxe2x80x9d, completing the path between the buffered Data nodes 108 and 110 and the coupling node 126. FET""s 116 and 118 are xe2x80x9coffxe2x80x9d, interrupting the feedback path that re-inforces storage. In this condition the state of the flip flop tracks the input Data signal until GB goes high again.
When the GB signal is high, the Q and QB outputs are maintained by a feedback loop composed of FETs 116 and 118 (which form a transmission gate), inverter 128 and inverter 130.
To illustrate the effect of a glitch on this circuit, suppose that the signal applied to the GB terminal is high, the Q output is high and the QB output is low. This means that nodes 132, 134, 136 and 138 are low and node 140 is high. Note that nodes 132 and 134 are the same physical node and that nodes 136 and 138 are the same physical node. If a glitch occurs at, for example, node 134 causing it to be driven high, inverter 130 will drive node 140 low. The signal at node 140 will be fed back to the input of inverter 128 which will drive nodes 136 and 138 high. If the feedback occurs before node 130 has a chance to recover from the glitch, node 134 will be driven high and an SEU will have occurred.
Glitches can occur in the latch, as discussed above, or they can be generated in logic outside the latch and propagate into the latch through a control line, for example, and cause an SEU.
Existing approaches to making circuits SEU-resistant include inserting resistors, capacitors or delay elements, such as inverters, in the feedback loop to slow the response of the loop to the glitch and thereby absorb it. Other approaches use redundancy and cross-coupled elements.
In general, in one aspect, the invention features a delay circuit comprising a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch.
Implementations of the invention may include one or more of the following. The network may comprise a P-type FET and an N-type FET. The gates of the two FETs may be coupled together and the drains of the two FETs may be coupled together. The source of the P-type FET may be coupled to the power source and the source of the N-type FET being coupled to ground. The channel of at least one of the FETs may be non-linear. The channel of the at least one of the FETs may include a jog. The jog may be a right angle. The second network may be an inverter. The voltage at the output of the second network may cross the threshold after a delay relative to the arrival of the glitch at the input to the first network. The delay may be determined by characteristics of the first network and characteristics of the second network.
In general, in another aspect, the invention features an SEU-resistant circuit comprising a gate having an input and an output and a feedback path from the output of the gate to the input of the gate. The feedback path comprises two or more delay elements. The gate and the two or more delay elements are configured to absorb a standard glitch at the input to the gate before it propagates through the feedback path to the input of the gate. The delay is spread among the gate and the two or more delay elements.
Implementations of the invention may include one or more of the following. The delay may be substantially evenly spread among the gate and the two or more delay elements. The delay elements may comprise balanced gates. The feedback path may further comprise a driver gate. The delay elements may comprise inverters. The number of delay elements may be even.
In general, in another aspect, the invention features an SEU-resistant circuit having a first state and a second state. The SEU-resistant circuit comprises a first flip-flop having a first state and a second state. The first flip-flop is configured to change state upon application of a signal to a first flip-flop signal input. The SEU-resistant circuit also comprises a second flip-flop having a first state and a second state equivalent to the first state and the second state of the first flip-flop. The second flip-flop is configured to change state upon application of a signal to a second flip-flop signal input. The first flip-flop is coupled to the second flip-flop such that the SEU-resistant circuit does not change from its first state to its second state unless the state of the first flip-flop agrees with the state of the second flip-flop. The SEU-resistant circuit includes an input to receive a signal to cause the SEU-resistant circuit to change states when the signal changes states. The input is coupled to the first flip-flop signal input. The input is coupled to the second flip-flop signal input through a delay circuit. The input is for one of a clock, reset or preset signal.
Implementations of the invention may include one or more of the following. The delay circuit may be non-inverting. The delay circuit may have a delay greater than the maximum expected glitch time.
In general, in another aspect, the invention features a transition NAND gate comprising two or more input nodes, an output node, and a state machine responsive to the two or more input nodes. The state machine is in a current state when signals applied to the respective input nodes have specified values. The state machine is capable of transitioning from a most recent current state to a state that is not a current state. The output node stores the current state of the state machine.
Implementations of the invention may include one or more of the following. The output node may have parasitic capacitance and the output node may store the current state in its parasitic capacitance. The state machine may comprise a supply-side FET for each input terminal. The gate of each supply-side FET may be connected to a respective input terminal. The supply-side FETs may be connected in series. The series-connected supply-side FETs may have a supply end and an output end. The state machine may comprise a ground-side FET for each input terminal. The gate of each ground-side FET may be connected to a respective input terminal. The ground-side FETs may be connected in series. The series-connected ground-side FETs may have a ground end and an output end. The output end of the series-connected supply-side FETs may be connected to the output end of the series connected ground-side FETs to form an output terminal.
The supply-side FETs may be P-type FETs, and the ground-side FETs may be N-type FETs. The state machine may be in a first current state when signals connected to the input nodes are all high and in a second current state when signals connected to the input nodes are all low.
In general, in another aspect, the invention features an SEU-resistant flip-flop comprising a Data input, a GB input, and a network responsive to signals applied to the Data input and the GB input. The network has a Q1 output which has the value of the signal applied to the Data input when the signal applied to the GB input is low, and a Q2 output which has the value of the signal applied to the Data input D seconds after the signal applied to the GB input is low. The Q1 output of the network is coupled to a Q1 node and the Q2 output of the network is coupled to a Q2 node. The SEU-resistant flip-flop includes a two-input one-output TAG. The output of the TAG is configured to change state only if the value of the signal on its first input is the same as the value of the signal on its second input. The first input of the TAG is coupled to the Q1 node. The second input of the TAG is coupled to the Q2 node. The output of the TAG is coupled to a QB node. The SEU-resistant flip-flop includes a first slow inverter having its input coupled to the QB node and its output coupled to the Q1 node, and a second slow inverter having its input coupled to the QB node and its output coupled to the Q1 node.
Implementations of the invention may include one or more of the following. The SEU-resistant flip-flop may further comprise a transmission gate, gated by the value of the signal in the GB node, in a signal path between the first slow inverter and the Q1 node, and a transmission gate, gated by the value of the signal on the GB node, in a signal path between the second slow inverter and the Q2 node. The SEU-resistant flip-flop may further comprise an inverter coupled to the QB node.
The TAG may comprise series-connected P-type FETs. The gate of a first P-type FET may be coupled to the Q1 node. The gate of a second P-type FET may be coupled to the Q2 node. The series-connected P-type FETs may have a supply end and a connection end. The TAG may comprise two series-connected N-type FETs. The gate of a first N-type FET may be coupled to the Q1 node and the gate of a second N-type FET may be coupled to the Q2 node. The series-connected N-type FETs may have a ground end and a connection end. The connection end of the series-connected N-type FETs may be coupled to the connection end of the series-connected P-type FETs and to the QB node.
The P-type FET coupled to the Q2 node may be at the connection end of the series-connected P-type FETs. The N-type FET coupled to the Q2 node may be at the connection end of the series-connected N-type FETs.
The network may comprise a first inverter having its input coupled to the GB input. The output of the first inverter may be coupled to a G node. A delay G may have its input coupled to the G node. The output of the delay G may be coupled to a G2 node. An inverter may have its input coupled to the G2 node and its output coupled to a GB2 node. A first transmission gate may be coupled between the Data input and the Q1 node and gated by the signals on the GB and G nodes, and a second transmission gate may be coupled between the Data input and the Q2 node and gated by the signals on the GB2 and G2 nodes. The delay G may comprise a first delay coupled in series with a second delay. A buffer may be coupled between the Data input and the first and second transmission gates.
In general, in another aspect, the invention features a method for reducing the vulnerability of a latch to single event upsets. The latch comprises a gate having an input and an output and a feedback path from the output to the input of the gate. The method comprises inserting a delay into the feedback path, and providing a delay in the gate.
Implementations of the invention may include one or more of the following. The gate may comprise a first FET having a channel and a second FET having a channel. The channel of the first FET and the channel of the second FET may be coupled at a node having a parasitic capacitance. Providing may comprise adjusting the characteristics of the channel of the first FET, the characteristics of the channel of the second FET and the parasitic capacitance of the node. Adjusting may comprise increasing the length of the channel of the first FET. Increasing may comprise making the channel non-linear. Making may comprise inserting a jog into the channel. The jog may be a right angle. The output of the gate may be coupled to a threshold device having an input, an output and a threshold. The output may have a first value when the input is less than the threshold and a second value when the input is greater than the threshold.
The method may further comprise adjusting the time constant and the threshold so that a glitch of length L1 at the input to the gate would not effect the output of the threshold device, a glitch of length L2, L1 less than L2 less than L3, would cause a pulse of length L4 less than L2 to appear at the output of the threshold device after a delay determined by the time constant and the threshold, and a glitch of length L5 greater than L3 would cause a pulse of length approximately L5 to appear at the output of the threshold device after a delay determined by the time constant and the threshold.